The present invention pertains to circuit testing and pertains particularly to the simultaneous display of data gathered using multiple data gathering mechanisms.
After manufacture, circuits are extensively tested to assure proper performance. For example, memory testers are used to test random access memories used in computers and other devices. Testing is typically performed by applying signals to and reading signals from pins of a device under test (DUT). Typically, the pins of a DUT function as address pins, data pins and control pins. The inputs and outputs of a DUT, including address pins, data pins and control pins are referred to herein as input/output pins or simply as pins. Some input/output pins are used just to input signals to the DUT. Other input/output pins are used just to output signals from the DUT. Other input/output pins are used both to input signals to the DUT and to output signals from the DUT.
Some test systems include programs that display waveforms for signals on the input/output pins of a DUT. Various mechanisms are used to capture signals for display.
For example, some test systems can process instructions in the test pattern and read the hardware state information to determine the waveform of signals to be placed on the inputs of the DUT. Similarly, some test systems can process instructions in the test pattern and read the hardware state information to determine the waveform of signals the test system expects to detect at the outputs of the DUT.
Some test systems make measurements at the inputs and/or outputs of a DUT in order to measure actual signals. This allows actual display of input and output signals for a DUT during a test. However, hardware constraints of test systems often limit the resolution at which data is displayed.
For example, a test system may simultaneously test multiple DUTs at one time. Simultaneous testing of up to 36 DUTs is typical. Each DUT has a multitude of input/output pins. DUTs with 64 pins or more are common. It would be time and/or cost prohibitive to use a voltage meter or oscilloscope to determine the exact voltage of every pin of every DUT being tested by a test system. For this reason, test systems typically include a compare circuit for each pin of each DUT being tested to compare the voltage at a pin with a test voltage. A voltage comparison typically can be performed at every pin once per test cycle. For increased voltage resolution of signals, several test cycles can be run and the voltage comparisons can be performed with different test voltages. For increased timing resolution of signals, several test cycles can be run and the voltage comparisons can be performed with different amounts of delay from the beginning of the test cycle.
In accordance with the preferred embodiment of the present invention, waveforms of input/output signals for a device under test (DUT) are simultaneously displayed. A user is presented with an interface that allows the user to specify different modes for capturing data for different input/output signals for the DUT. Data for the different input/output signals are captured in accordance with different data capture mechanisms dependent upon the different modes specified by the user. Based on the data, waveforms for each of the different input/output signals are simultaneously displayed.